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CPLDNEW
- 用maxplus2实现的一种通用逻辑模块，背景是一个基于dsp的嵌入式开发板，上面的逻辑模块全用cpld实现。此模块可以供以后的嵌入式开发作参考。-maxplus2 achieved using a common logic modules, background is a DSP-based embedded development board, the above logic modules throughout cpld achieve. This module can be embedd
zlgusb
- 周立功的USB大容量存储开发板带CPLD的代码D的源码-weeks meritorious USB Mass Storage Development strip CPLD the source code D.
3-8-yimaqi
- 38译码器程序，采用verilog语言编写，在CPLD开发板上经过验证，希望对大家有用-38 decoder program, using verilog language, proven in the CPLD development board, we hope to be useful
LCD12864
- lcd12864程序，采用Verilog语言编写，在CPLD开发板上经过验证，正确无误，实现显示英文的功能，希望对大家有用-lcd12864 procedure for the Verilog language, proven in the CPLD development board, correct, implement the function displayed in English, we hope to be useful
juzhenjianpan
- 矩阵键盘程序，采用Verilog语言编写，在CPLD开发板上经过验证，正确无误，希望对大家有用-Matrix Keyboard Program, the use of Verilog language, the CPLD development board verified and correct, we hope to be useful
PWMPLED
- 程序正确无误，采用Verilog语言编写，并在CPLD开发板上经过验证，希望对大家有用-Program is correct, the use of Verilog language, and proven in the CPLD development board, we hope to be useful
chufaqi
- 除法器程序，采用Verilog语言编写，并在CPLD开发板上经过验证，正确无误，希望对大家有用-Divider procedure for the Verilog language, and CPLD development board verified and correct, we hope to be useful
fengmingqi
- 蜂鸣器程序，采用Verilog语言编写，在CPLD开发板上经过验证，希望对大家有所帮助-Buzzer procedure for the Verilog language, proven in the CPLD development board, we hope to help
Displayer
- VHDL编写的针对八段数码管的显示译码电路。实现动态扫描输出小时、分钟和秒。是基于CPLD开发板设计的一个数字钟的一部分。-Programmed with VHDL.The decoding and displaying circuit for 8-segments displayer.It outputs the data of hour,minute and second in order with dynamic scaning method.It is one of my total 9
DIP-switches-and-LED-display
- 拨码开关管和LED显示，在CPLD开发板上实现拨码开关管和LED显示-DIP switches and LED display
MAX_II_board_schematics
- max ii CPLD 开发板的原理图。 CPLD硬件开发好资料-schematic of max ii demo board
CPLD
- epm240GT100C3开发板原理图，希望对你们有用。-epm240GT100C3 Schematic diagram，I hope it is useful to you
MAX_II_RevC_brd
- Altera CPLD开发板原理图和PCB -Altera CPLD
fVerrilog_Devr
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
DSPPCPLDkaifabandianluyuanlitu
- 本文件是DSP+CPLD开发板电路原理图，是从事电路开发研究的经典电路哈，可以直接拿来画电路板！-This document is DSP+CPLD development board circuit schematic, is engaged in the research and development of circuit classic circuit Kazakhstan, can be directly used to draw the board!
FPGA_CPLD-SHC
- FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考-FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design
VHDL
- 基于VHDL语言和CPLD开发板的，分频电路电路的开发。-Based on VHDL and CPLD development board, divider circuit circuit development.
BCD_ok-BCD
- Verilog 4位计时器,可以在CPLD开发板上成功运行-Verilog CPLD FPGA
Verilog_prj
- 特权同学BJ-EPM240 CPLD开发板配套视频源码文件，ex1~ex15全，是入门Verilog的首选。-Privileged students BJ-EPM240 CPLD development board supporting the video source files, ex1 ~ ex15 whole, is the first choice of entry Verilog.
0001_EPM3064最小系统模块_带JTAG_LED_2mm插针
- EMP3064的开发板板，原理图，verilog例子，板子说明，规格书，全套资料(EMP3064 development board, schematics, Verilog examples, board instructions, specifications, a full set of information)